Goals for the Week:
- Finish Cellular Automation Hardware design in Verilog
- Create mid-project presentation
Progress:
- I still have not finished the hardware for automation
- Calculating border conditions in hardware is much less trivial than doing so in software
- Running the calculations in parallel is more difficult than what we did for the julia-set creation
- The presentation will be finished shortly
Current Challenge:
- Running a parallel calculation with multiple values that are subject to previous change is causing me the following problems:
- Timing. I am trying to optimize the amount of time needed for each generation to be computed by having hardware specific to each cell.
- Hardware usage. I am using specific hardware for each cell, and each cell also has 2 flip-flops per cell. Also, because cells all depend on the previous values of other cells, wires between previous flip flop values are required as well.
- I don’t see these as huge problems, but I will bring them up in our presentation tomorrow to get ideas from the rest of the class on how to solve them
Plan for next week:
- Finish the hardware implementation by Wednesday.
- Begin implementing with Sarah’s BRAM on Wednesday, and begin displaying the output of the cellular automation via VGA
- Spend the weekend debugging my calculation implementation in hardware
- I won’t be able to debug except for synthesize errors because I won’t be able to see the output until then